US Citizen or US Person (Green Card) Required
Length of Assignment:
6+ Month Contract
Location:
Fully On-site in San Jose, CA or Austin, TX. 5 days a week.
Interviews:
2 Stage Interviews process
Start date:
ASAP
Role:
- This position represents a chance to join a highly talented team, at the forefront of chip design, where you’ll be working on cutting-edge verification techniques and see your work drive real innovation in the company’s flagship mobile phones. You’ll be working with, and learning from, some of the brightest minds in semiconductors, where your contributions will make a visible impact on next-generation technology.
- Candidates must have recent, hands-on experience in Formal Design Verification. This role is open to junior through senior-level professionals, provided they can demonstrate strong, practical and production level expertise in Formal Design Verification.
- Based onsite in San Jose, CA OR Austin, TX – the position requires 5 days per week onsite. While initially set for 6 months, there is a strong chance of long-term opportunities and extensions are likely.
Responsibilities:
- Perform Sequential Equivalence Checking (SEQ) for clock gating, datapath, and RTL transformations.
- Write assertions, assumptions, constraints, and cover properties for GPU IP blocks.
- Develop formal verification setup using System Verilog modules and Assertions
- Run formal verification checks, analyze the results, and debug any issues.
- Develop and enhance constraints, checks, and cover points to achieve verification quality.
- Verify GPU design blocks using formal verification approaches like sequential equivalence checking, property-based feature verification and datapath verification using C models.
- Analyze and deploy formal convergence techniques like abstraction, blackboxing and design reductions.
- Work closely with cross-functional teams, including design, architecture, and software teams, to ensure that verification efforts are aligned with project goals and requirements.
- Participate in the development and improvement of verification methodologies, tools, and flows to increase efficiency and effectiveness of verification efforts.
- Adhere to project execution and planning approaches using Confluence, JIRA and relevant techniques.
- Create and maintain documentation for formal verification test plans, convergence reports, complexity analysis reports and results.
- Responsible in driving formal verification tasks & report to project verification leads as required
Skills And Qualification Requirements:
- BSEE, Computer Engineering, or Computer Science bachelor’s degree and a minimum of 3+ years of experience
- Masters or Ph.D. degree preferred
- Good understanding of GPU and/or CPU design architecture
- Hands-on experience in developing formal based datapath verification setups using RTL & C Models
- Hands-on experience in developing formal property-based feature verification setups
- In-depth expertise on proof depth and convergence analysis for formal setups
- Strong experience or exposure to System Verilog (SV), System Verilog Assertion (SVA) coding skills, and Sequential Equivalence Checking (SEQ) is required
- Experience in developing formal verification setups is a must
- Experience in developing constrained random testbenches is preferred
- Experience with formal verification tools such as VC Formal, Jasper Gold, or Questa Formal is preferred.
- Experience with Digital RTL design; GPU/parallel architecture/Shaders is a plus.
- Scripting skills with Python/Perl/TCL is a plus
- Excellent communication skills and be able to work with cross-functional teams to execute verification plan
