Design Verification Engineer (IP Team) - Austin

The Company

Our client is a global leader in technology and has been transforming the electronics we use every day - TVs, smartphones, wearable devices, tablets, etc. since 1969. Since being established, our client has grown into a global brand and is now one of the leading technology companies in the world and a reputable, globally recognized brand.

The Role

As a member of the System IP team you will contribute to the functional verification of System IP including coherent interconnect. You will work with the DV team and designers to build verification environments. You will assist in the development of UVM sequences, tests, scoreboards, monitors and checkers You will define/plan/implement/execute functional verification strategy of complex System IP designs as well as develop feature-based test plans. You will build verification environments, develop UVM sequences, write SVA assertions as well as regression triaging and debugging.

The Individual

As the ideal candidate you will have the following skill and experience:

  • 12+ years of experience in Verification
  • Experience with SystemVerilog and UVM
  • Previous experience executing verification strategy of complex IP designs
  • Previous experience developing UVM sequences, tests, and designers to build out verification environments
  • You will have the knowledge and understanding to delve into the details of Coherent fabric & LLC Design
  • Proficient in Python or C++
  • Good knowledge of memory subsystem, including interconnect, last-level cache, coherency


Location: Austin, TX (The role is hybrid and will be onsite 3x per week)

Salary: $85-95/hour DOE on a W2 basis

Contact Details:

ConSol Partners

We are a leading consultancy for expansion in communications, content and emerging technology markets. We work in collaboration with growing organizations on exclusive assignments to find them the best talent in the industry